(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memory).
(2) Description of Prior Art
Self-alignment of various components in a device can help reduce tolerances and improve the packing density of chips. In flash EEPROM memory cells self-alignment of the floating gates to diffusion is particularly important, and methods have been devised to provide this self-alignment. A major problem, which is eliminated by the invention, is that traditional methods of foiling self-aligned floating gate to diffusion structures inherently generate catastrophic defects. The efficiency of operations in flash memory cells is strongly dependent on the control gate to floating gate coupling ratio. In traditional methods of forming self-aligned floating gate to diffusion structures flash memory cells process related reductions of the coupling ratio occur. Such process related reductions in the coupling ratio do not occur in the method of the invention.
A conventional method for forming a traditional floating gate structure, in which the floating gate is self-aligned to the diffusion, is advantageously described with reference to FIGS. 1a–10b, of which FIGS. na, n=1-10, present top views and the rest show cross-sectional views. FIGS. 1a and 1b show the structure just before the etching steps to form isolation regions. To arrive at this stage, a gate oxide layer, 4, of thickness about 90 Angstroms is formed over the surface of a crystalline silicon region, 2, and a conductive polysilicon layer, 6, about 600 Angstroms thick and silicon nitride layer, 8, about 1600 Angstroms thick are successively formed over the oxide layer. Next a photoresist layer is formed and patterned into parallel stripes, 10. The direction of the stripes, 10, is denoted the horizontal direction and the direction perpendicular to the stripes is denoted the vertical direction. Successively etching the silicon nitride layer, the polysilicon layer, the oxide layer and the silicon region forms the shallow trench isolation (STI) regions 12, after which the photoresist layer 10 is removed and the structure is as shown in FIGS. 2a and 2b. The STI regions define the active regions, 14, upon which they border and also, simultaneously, define the horizontal borders of the polysilicon layer that overlie the active regions and that will constitute the floating gates, providing the self-alignment of the floating gates to the diffusion, i.e. the silicon region of the active regions. Next, the STI are filled with oxide. First a silicon oxide liner layer, 16, about 200 Angstroms thick is grown over the sides and bottom of the STI. Since the oxidation rate of polysilicon is larger than of crystalline silicon, an even thicker silicon oxide layer, 18, is grown, at the same time, over the exposed surfaces of the polysilicon layer. As a result of the liner oxidation step the polysilicon sides, 20, are rounded and do no longer entirely cover the silicon region of the active regions. This results in a reduction in the control gate to floating gate coupling ratio and thus to a decrease in the efficiency of device operation. Furthermore, the polysilicon no longer protects the silicon region corner, which consequently can be damaged in the polysilicon etching process that follows. Next an HDP oxide is deposited to a depth of about 6500 Angstroms filling the STI. A CMP process is then performed that; since the oxide CMP cannot be precisely controlled, can at times lead to the undesirable situations shown in FIGS. 3a, 3b, 4a and 4b. The situation shown in FIG. 3b, referred to as the excess case, occurs when insufficient material is removed in the CMP process. Thus, the thickness of the HDP oxide layer, 22, and of the silicon nitride layer, 24, are significantly larger than nominal. In FIG. 4b, the situation shown, referred to as the deficiency case, occurs when too much material is removed in the CMP process. In this case the thickness of the HDP oxide layer, 26, and of the silicon nitride layer, 28, are significantly smaller than nominal. An oxide dip etch step is performed next in which the thickness of the oxide layers are reduced, to achieve the structures shown in FIGS. 5a and 5b for the excess case and FIGS. 6a and 6b for the deficiency case. In the excess case the HDP oxide, 30, extends above the level of the polysilicon layer, which is therefore not exposed. The HDP oxide, 32, in the deficiency case just covers the STI region and as a consequence the oxide grown on the sides of the polysilicon layer, 20, is also removed by the oxide dip etch. After removing the silicon nitride layer, a photoresist layer, 34, is patterned into stripes in the vertical direction to further define the floating gates. Before a polysilicon etching step the cross sections in regions between the photoresist stripes, regions where polysilicon will be removed, is as shown in FIGS. 7a and 7b for the excess case and FIGS. 8a and 8b for the deficiency case. In each case significant defects arise as indicated in FIGS. 9a and 9b for the excess case and 10a and 10b for the deficiency, which show the corresponding cross-sections after the polysilicon etch. Polysilicon residues, 34, are found, in the excess case, adjacent to the oxide grown on the polysilicon sides where the residues were protected from the silicon etch. The defect in the deficient case, 36, is damage to the silicon region where there was no polysilicon layer or polysilicon oxide layer during the polysilicon etch. Both defects are essentially catastrophic to the device and it is a primary objective of the invention to provide a method of forming self-aligned floating gate to diffusion structures in which these defects are not generated. It is a further primary objective of the invention to provide a method of forming self-aligned floating gate to diffusion strictures in which process related reductions in the floating gate to control gate coupling ratio do not occur.
Chu et al. U.S. Pat. No. 6,403,494 discloses a method of forming a split-gate flash memory cell with the floating gate self-aligned to the shallow trench isolation (STI). The self-alignment is made possible, in one embodiment, by the use of an anti-reflective coating and, in another embodiment, by the use of a low-viscosity material. Lin et al. U.S. Pat. No. 6,358,796 teaches a method to fabricate a split-gate flash memory cell with self-aligned STI without the intrusion of a smiling gap. U.S. Pat. No. 6,245,685 to Sung et al. shows a method for forming a square oxide stricture or a square floating gate stricture without rounding of corners. U.S. Pat. No. 6,140,182 to Bergemont discloses a method for reducing the spacing between adjacent floating gates of flash memory arrays. Camerlenghi, U.S. Pat. No. 5,330,938, shows a method of making s non-volatile split-gate EEPROM cell with self aligned field insulation.